It is well known in the art of digital data transfer that high data rates can be achieved by transferring data over a parallel data bus. For a given bus rate, the bus bandwidth measured in bits-per-second is equivalent to the bus rate times the number of data signals comprising the parallel data bus.
A typical system might include a number of modules which interface to a backplane module. The modules intercommunicate via a parallel bus on the backplane module. A transmitting module transmits data over the backplane bus synchronous with a clock on the transmitting module; thus, all transitions on all signal lines on the backplane bus leave the transmitting module in a synchronous relationship to the clock on the transmitting module. Receiving modules also implement a clock at the bus rate, and receive the data on the backplane bus synchronous to the receive clock.
In such prior art systems, it is necessary to ensure that the receive clocks have a specific phase relationship to the transmit clock to ensure proper data recovery. For example, the transmit clock may be transmitted to the receiving modules over the backplane, the receive clocks then being derived from it.
In any system where a parallel bus is implemented on a backplane module, there will be some amount of time skew between the bus signals themselves and between the bus signals and the receive clock at the destination, since the signals are subject to transmission delays due to capacitive loading and line lengths. In low speed systems, this time skew is a small percentage of the overall clock period; thus, as long as the receive clock is in phase with the transmit clock, the skew does not interfere with data recovery and can therefore be ignored.
Parallel buses, however, reach certain limitations as clock rates are increased. In particular, where a high-speed parallel bus is implemented on a backplane module such that the various signals making up the parallel bus must travel a significant distance between their source and destination, transmission delays on the data signals due to loading variations and line lengths cause relatively large time skews between the signals themselves and between the signals and receive clocks. As these time skews become a significant percentage of the clock frequency, they can no longer be ignored. Such time skews can preclude direct use of the receive clock for clocking the bus signals into a receive register or latch, since setup and/or hold time violations might occur, causing faulty data reception. The skew problem becomes more pronounced at higher clock rates, because as clock rates increase, data signals need travel only a short distance before these difficulties are encountered.
Prior art solutions to the skew problem typically center on minimizing the bus skew seen at the receiving module, through implementation, for example, of expensive backplane module manufacturing techniques employing impedance matching of the data lines constituting the parallel bus, or by minimizing the allowable length of the parallel bus. As bus clock rates have continued to increase, the expense and limitations of these prior solutions have become unacceptable.